1. Field of the Invention
The present invention relates to the design of optical transceivers. More specifically, the present invention relates to a multi-dimensional wavelength-division-multiplexing (WDM) transceiver that permits multiple WDM transceivers to be co-located on a single semiconductor chip.
2. Related Art
Optical transceivers convert high-speed electrical signals into optical signals (and vice-versa) for transmission through fiber optic cables. Optical transceivers are also commonly used for communicating data between electronic components within a datacenter. These optical transceivers populate the boards and cards within a data communications or telecommunications chassis, and communicate to other chips within the chassis.
One factor that limits the capacity of optical transceivers, and hence the communication capacity between electronic components within the system, is the total number of lasers or optical modulators that can be integrated into the transceiver package. Since the cost of the transceiver is a function of the cost of the active optical components and the packaging of these components, it is desirable that as many optical components be integrated onto one semiconductor chip as possible. This is also of particular importance as the performance of the transceivers increases.
In high-end systems applications, a large gap exists between the I/O bandwidth density required on an electronic chip versus what present-day optical interconnect technology is capable of delivering. Although significant advances in off-chip electrical I/O and signaling density have been achieved for short transmission lengths, off-chip electrical I/O has many disadvantages, including high electrical power dissipation and limited transmission length (approximately one meter).
An optical interconnect solution is desirable to transport very large aggregate bandwidths over many meters. Unfortunately, existing optical technology cannot meet the bandwidth requirements in a package comparable to the size of the chip. For example, electrical interconnect density can be as high as 4 Tb/s in a one square-centimeter chip. However, existing optical solutions can only achieve 10-100 times smaller bandwidth onto such a chip. The current optical interconnect solutions have fallen far behind electrical interconnect densities, and the gap continues to widen.
Another limitation of the existing optical interconnect technologies is that they have traditionally been based on technology platforms that differ significantly from those for an electronic chip (e.g. III-V compound semiconductor photonics versus silicon-based circuits). Options to integrate these different technologies together require a hybrid or a heteroepitaxy materials integration solution. However, neither of these techniques has been proven at wafer-level integration. If such integration is to be practiced on a large scale, wafer-level integration is necessary to facilitate a low-cost solution for optical interconnects and to deliver prices competitive with electrical interconnects.
Another issue is that III-V photonics has historically been based on forward-biased devices which operate in an emitting geometry. These devices are ideal in applications where the total number of components is low. However, in applications requiring a large number of emitter components for high interconnect density, the device reliability of these forward-biased devices is a drawback. Component failure is so severe that the resulting chip interface is rendered useless.
Yet another issue is that the optical and electrical technologies are governed by different technology roadmaps and hence don't share a common scaling parameter. This issue ultimately makes it very difficult for system designers to anticipate the design of future generations of optical transceivers.
Hence, what is needed is an optical transceiver without the problems described above.